soft error rate

Moshe Valdman from Israel wrote this question: In a telecom system we have many memories and FPGAs Theoretically we should have quite high failure rate related to "single event upset". I suspect we indeed have such failures, but these could also be just SW "bugs". I have difficult time convincing developers to add ECC, CRC, parity and other means to correct or at least detect such temporary failures. Can you share ideas on how to estimate actual field failures rate related to SEUs and how to quantify the cost? Charlie Slayman, our Ops SER Expert wrote back: Yes, you will have soft errors if you have memory and FPGAs.  Typical rates for SRAM and flops vary between 100 to 1000 FIT per Mb or Mflop.  DRAM rates are much lower, around 100 FIT/Gb.  Check out Slide 25 of my …

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